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document number: mc33880 rev. 8.0, 5/2012 freescale semiconductor technical data freescale semiconductor, inc. reserves t he right to change the detail specifications, as may be required, to permit improvements in the design of its products. ? freescale semiconductor, inc. , 2009-2012. all rights reserved. configurable octal serial switch with serial peripheral interface i/o the 33880 device is an 8-output hardware configurable high side/ low side switch with 8-bit serial input control using the serial peripheral interface (spi). two of the out puts can be controlled directly via microcontroller for pulse-width modulation (pwm) applications. the 33880 controls various inductive or incandescent loads by directly interfacing with a microcontroller. the circuit's innovative monitoring and protection features include very low standby currents, ?cascadabl e? fault reporting, internal 40 v output clamping for low side configur ations, internal -20 v output clamping for high side configurations , output specific diagnostics, and independent shutdown of outputs. features ? designed to operate 5.5 v < v pwr < 24.5 v ? 8-bit spi for control and fault reporting, 3.3/ 5.0 v compatible ? outputs are current limited (0.8 a to 2.0 a) to drive incandescent lamps ? output voltage clamp is +45 v (typical) (low side drive) and -20 v (typical) (high side drive) during inductive switching ? internal reverse battery protection on v pwr ? loss of ground or supply will not energize loads or damage ic ? maximum 5.0 a i pwr standby current at 13 v v pwr up to 95 c ?r ds(on) of 0.55 at 25 c typical ? short circuit detect and current limit with autoretry ? independent over-temperature protection ? 32-pin soicw has pins 8, 9, 24, and 25 grounded for thermal performance figure 1. 33880 simplified application diagram high/low side switch eg suffix (pb-free) 98asb42345b 28-pin soicw 33880 ordering information device (for tape and reel, add an r2 suffix) temperature range (t a ) package MC33880PEG -40 c to 125 c 28 soicw mc33880pew 32 soicw ew suffix (pb-free) 98arh99137a 32-pin soicw all output switches are high- or low-side configurable v pwr 33880 spi i/o pwm mcu mot high-side h-bridge low-side 5.0 v 5.0 v v s d1 d2 d4 d5 d6 d7 s8 d3 en vdd vpwr gnd cs sclk di do in5 in6 s1 s2 s4 d8 s5 s6 s7 s3
analog integrated circuit device data 2 freescale semiconductor 33880 internal block diagram internal block diagram figure 2. 33880 simplifi ed internal block diagram spi bit 4 in5 spi bit 0 ov , por , sleep ~50 a ~50 a d8 d7 d4 d3 d2 d5 spi and logic interface limit open/short comparator threshold ~1.5 v open/short control drive gate threshold open/short comparator open load detect current ~650 a tlim + ? + ? + ? + ? current limit gate drive control open load detect current _ + ~650 a cs __ sclk di do ~50 a en vdd ~50 a in5 in6 internal bias charge pump overvoltage shutdown / por sleep state tlim current _ + ~1.5 v open/short enable vpwr gnd d1 typical of all 8 output drivers s1 drain outputs s2 s3 s4 s7 s8 source outputs d6 s5 s6 drain outputs source outputs
analog integrated circuit device data freescale semiconductor 3 33880 pin connections pin connections figure 3. 28-pin connections table 1. soicw 28-pin definitions pin number pin name definition 1 gnd digital ground. 2 vdd logic supply voltage. logic supply must be switched off for low current mode (v dd below 3.9 v). 3, 4 s8 output 8 mosfet source pins. 5 d8 output 8 mosfet drain pin. 6 s2 output 2 mosfet source pin. 7 d2 output 2 mosfet drain pin. 8 s1 output 1 mosfet source pin. 9 d1 output 1 mosfet drain pin. 10 d6 output 6 mosfet drain pin. 11 s6 output 6 mosfet source pin. 12 in6 pwm direct control input pin for out put 6. in6 is ?or? with spi bit. 13 en enable input. allows control of outputs. active high. 14 sclk spi control clock input pin. 15 di spi control data input pin from mcu to the 33880. logic [1] activates output. 16 cs spi control chip select input pin from mcu to the 33880. logic [0] allows data to be transferred in. 17 in5 pwm direct control input pin for out put 5. in5 is ?or? with spi bit. 18 s5 output 5 mosfet source pin. 19 d5 output 5 mosfet drain pin. 20 d3 output 3 mosfet drain pin. 21 s3 output 3 mosfet source pin. 22 d4 output 4 mosfet drain pin. 23 s4 output 4 mosfet source pin. 24 d7 output 7 mosfet drain pin. 25, 26 s7 output 7 mosfet source pins. 27 vpwr power supply pin to the 33880. vpwr has internal reverse battery protection. 28 do spi control data output pin from the 33880 to the mcu. do = 0 no fault, do = 1 specific output has fault. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 28 27 26 25 24 23 22 21 20 19 18 17 16 do vpwr s7 s7 d7 s4 d4 s3 d3 d5 s5 in5 cs di gnd vdd s8 s8 d8 s2 d2 s1 d1 d6 s6 in6 en sclk
analog integrated circuit device data 4 freescale semiconductor 33880 pin connections figure 4. 32-pin connections table 2. soicw 32-pin definitions pin number pin name definition 1 gnd digital ground. 2 vdd logic supply voltage. logic supply must be switched off for low current mode (v dd below 3.9 v). 3, 4 s8 output 8 mosfet source pins. 5 d8 output 8 mosfetdrain pin. 6 s2 output 2 mosfet source pin. 7 d2 output 2 mosfet drain pin. 8, 9, 24, 25 tgnd thermal ground pins are connected internally to the s ubstrate of the die and are used for heat transfer. connect thermal ground pins to the pc b ground and ground plane for heat sinking. 10 s1 output 1 mosfet source pin. 11 d1 output 1 mosfet drain pin. 12 d6 output 6 mosfetdrain pin. 13 s6 output 6 mosfet source pin. 14 in6 pwm direct control input pin for out put 6. in6 is ?or? with spi bit. 15 en enable input. allows control of outputs. active high. 16 sclk spi control clock input pin. 17 di spi control data input pin from mcu to the 33880. logic [1] activates output. 18 cs spi control chip select input pin from mcu to the 33880. logic [0] allows data to be transferred in. 19 in5 pwm direct control input pin for out put 5. in5 is ?or? with spi bit. 20 s5 output 5 mosfet source pin. 21 d5 output 5 mosfet drain pin. 22 d3 output 3 mosfet drain pin. 23 s3 output 3 mosfet source pin. 26 d4 output 4 mosfet drain pin. 27 s4 output 4 mosfet source pin. 28 d7 output 7 mosfet drain pin. 29, 30 s7 output 7 mosfet source pins. 31 vpwr power supply pin to the 33880. vpwr has internal reverse battery protection. 32 do spi control data output pin from the 33880 to the mcu. do = 0 no fault, do = 1 specific output has fault. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 do vpwr s7 s7 d7 s4 d4 tgnd tgnd s3 d3 d5 s5 in5 cs di gnd vdd s8 s8 d8 s2 d2 tgnd tgnd s1 d1 d6 s6 in6 en sclk
analog integrated circuit device data freescale semiconductor 5 33880 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit vdd supply voltage (1) v dd -0.3 to 7.0 v dc cs , di, do, sclk, in5, in6, and en (1) ? -0.3 to 7.0 v dc vpwr supply voltage (1) v pwr -16 to 50 v dc drain 1 ? 8 (2) 5.0 ma i out 0.3 a ? -18 to 40 v dc source 1 ? 8 (3) 5.0 ma i out 0.3 a ? -28 to 40 v dc output voltage clamp low-side drive (4) v oc 40 to 55 v dc output voltage clamp high-side drive (4) v oc -15 to -25 v dc output clamp energy (5) e clamp 50 mj esd voltage (6) human body model machine model v esd1 v esd2 2000 200 v storage temperature t stg -55 to 150 c operating case temperature t c -40 to 125 c operating junction temperature t j -40 to 150 c maximum junction temperature ? -40 to 150 c power dissipation (t a = 25 c) (7) 28 soic, case 751f-05 32 soic, case 1324-02 p d 1.3 1.7 w thermal resistance, junction-to-ambient, 28 soic, case 751f-05 r ja 94 c/w thermal resistance, junction-to-ambient, 32 soic, case 1324-02 thermal resistance, junction-to-ther mal ground leads, 32 soic, case 1324-02 r ja r jl 70 18 c/w peak package reflow temperature during reflow (8) , (9) t pprt note 9 c notes 1. exceeding these limits may cause malf unction or permanent damage to the device. 2. configured as low-side driver wi th 300 ma load as current limit. 3. configured as high-side driver with 300 ma load as current limit. 4. with outputs off and 10 ma of test current for low-side driver, 30 ma test current for high-side driver. 5. maximum output clamp energy capability at 150 c junction temperature using single non-repetitive pulse method. 6. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ), and esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ). 7. maximum power dissipation with no heatsink used. 8. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 9. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33880 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 16 v, -40 c t c 125 c unless otherwise noted. typical values, where applicable, reflect t he parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit power input supply voltage range fully operational v pwr(fo) 5.5 ? 24.5 v supply current i pwr(on) ? 8.0 14 ma sleep state supply current (vdd and en = 0 v, vpwr = 16 v) temperature = -40c to 95c temperature = 95c to 125c i pwr(ss) ? ? 2.0 5.0 5.0 20 a overvoltage shutdown v ov 25 27 30 v overvoltage shutdown hysteresis v ov(hys) 0.15 0.8 2.5 v logic supply voltage v dd 4.75 ? 5.25 v logic supply current i dd 0.5 2.6 4.0 ma logic supply undervoltage lockout threshold v dd(unvol) 3.9 4.3 4.7 v logic supply undervoltage hysteresis v dd(unvol-hys) 100 150 300 mv power output drain-to-source on resistance (v pwr = 16 v) i out = 0.25 a, t j = 125 c i out = 0.25 a, t j = 25 c i out = 0.25 a, t j = -40 c r ds(on) ? ? ? 0.75 0.55 0.45 1.1 0.85 0.80 output self-limiting current high-side and low-side configurations v pwr = 16 v i out(lim) 0.8 1.4 2.0 a output fault detect threshold (10) , (11) outputs programmed off v outth(f) 1.0 ? 3.0 v output off open load detect current (10) outputs programmed off i oco 0.30 0.55 1.0 ma output clamp voltage low-side drive i d = 10 ma v oc(lsd) 40 45 55 v output clamp voltage high-side drive i s = -30 ma v oc(hsd) -15 -20 -25 v output leakage current high-side and low-side configuration v dd = 0 v, v ds = 16 v i out(lkg) ? 1.0 7.0 a overtemperature shutdown (11) t lim 155 ? 185 c overtemperature shutdown hysteresis (11) t lim(hyst) 5.0 10 15 c notes 10. output fault detect thresholds with outputs programmed off. output fault detect threshold are the same for output open and s horts. 11. this parameter is guaranteed by design but is not production tested.
analog integrated circuit device data freescale semiconductor 7 33880 electrical characteristics static electrical characteristics digital interface input logic voltage thresholds (12) v inlogic 0.8 ? 2.2 v in5, in6, and en input logic current in5, in6, en = 0 v i in5, in6, en -10 ? 10 a in5, in6, and en pull-down current 0.8 v to v dd i in5, in6, en 30 45 100 a sclk, di, and tri-state do input 0 v to v dd i sck, si, triso -10 ? 10 a cs input current cs = v dd i ics -10 ? 10 a cs pull-up current cs = 0 v i ics -30 ? -100 a do high-state output voltage i do-high = -200 a v dohigh v dd - 0.8 ? v dd v do low-state output voltage i do-high = 1.6 ma v dolow ? ? 0.4 v input capacitance on sclk, di, tri-state do, in5, in6, en (13) c in ? ? 20 pf notes 12. upper and lower logic threshold voltage levels apply to di, cs , sclk, in5, in6, and en. 13. this parameter is guaranteed by design but is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 16 v, -40 c t c 125 c unless otherwise noted. typical values, where applicable, reflect t he parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33880 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 9.0 v v pwr 16 v, -40 c t c 125 c unless otherwise noted. typical values, where applicable, reflect t he parameter?s approximate average value with v pwr = 13 v, t a = 25 c. characteristic symbol min typ max unit power output timing output slew rate low-side configuration (14) r l = 620 t r 0.1 0.5 1.2 v/ s output slew rate low-side configuration (14) r l = 620 t f 0.1 0.5 1.2 v/ s output slew rate high-side configuration (14) r l = 620 t r 0.1 0.3 1.2 v/ s output slew rate high-side configuration (14) r l = 620 t f 0.1 0.3 1.2 v/ s output turn on delay time, high-side and low-side configuration (15) t dly(on) 1.0 15 50 s output turn off delay time, high-side and low-side configuration (15) t dly(off) 1.0 30 100 s output fault delay time (16) t fault 100 ? 300 s digital interface timing recommended frequency of spi operation ? ? 4.0 6.0 mhz required low state duration on v dd for reset (17) v dd 0.2 v t reset ? 4.0 10 s falling edge of cs to rising edge of sclk (required setup time) t lead 100 ? ? ns falling edge of sclk to rising edge of cs (required setup time) t lag 50 ? ? ns di to falling edge of sclk (required setup time) t di(su) 16 ? ? ns falling edge of sclk to di (required hold time) t di(hold) 20 ? ? ns di, cs , sclk signal rise time (18) t r(di) ? 5.0 ? ns di, cs , sclk signal fall time (18) t f(di) ? 5.0 ? ns time from falling edge of cs to do low impedance (19) t do(en) ? ? 60 ns time from rising edge of cs to do high impedance (20) t do(dis) ? ? 60 ns time from rising edge of sclk to do data valid (21) t valid ? 25 60 ns notes 14. output rise and fall time res pectively measured across a 620 resistive load at 10 to 90 percent and 90 to 10 percent voltage points. 15. output turn on and off delay time measured from 50 percent rising edge of cs to 90 and 10 percent of initial voltage. 16. duration of fault before fault bit is set. duration between access times must be greater than 300 s to read faults. 17. this parameter is guaranteed by design but is not production tested. 18. rise and fall time of incoming di, cs , and sclk signals suggested for design considerat ion to prevent the occurrence of double pulsing. 19. time required for output status data to be available for use at do pin. 20. time required for output status data to be terminated at do pin 21. time required to obtain valid data out from do following the rise of sclk.
analog integrated circuit device data freescale semiconductor 9 33880 electrical characteristics timing diagrams timing diagrams figure 5. spi timing diagram figure 6. valid data delay time and valid time test circuit figure 7. enable and disable time test circuit figure 8. switching time test circuit t do(dis) 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t di(su) t di(hold) t valid t lag cs sclk di do msb in msb out lsb out 0.7 v dd 0.2 v dd t do(en) do c l = 200 pf v dd = 5.0 v sclk 33880 under te s t note: c l represents the total capacitance of the test fixture and probe. do c l = 200 pf r l = 1.0 k cs 33880 under te s t note: c l represents the total capacitance of the test fixture and probe. v dd = 5.0 v v pull-up = 2.5 v output c l r l = 620 v pwr = 13 v cs 33880 under te s t note: c l represents the total capacitance of the test fixture and probe. v dd = 5.0 v
analog integrated circuit device data 10 freescale semiconductor 33880 electrical characteristics timing diagrams figure 9. valid data delay time and valid time waveforms figure 10. enable an d disable time waveforms figure 11. turn -on/off waveforms (low-to-high) t f(di) t r(di) 0.2 v dd 0.7 v dd 0.2 v dd 0.7 v dd t valid t r(do) v ol v oh v ol v oh t dly(hl) t dly(lh) 0.2 v dd 0.7 v dd (2.5 v) 0 5.0 v < 50 ns 50% < 50 ns do sclk (high-to-low) do 90% t r(di) t f(di) v oh t so(dis) 0 5.0 v do t do(dis) t do(en) t do(dis) t do(en) (tri-state to low) 0.7 v dd 0.2 v dd (2.5 v) < 50 ns < 50 ns cs 90% do (tri-state to high) 10% 10% 90% 10% v tri-state v tri-state 90% t r(di) t f(di) v tri-state v oh t so(dis) 0 5.0 v do t do(dis) t do(en) t do(dis) t do(en) (tri-state to low) 0.7 v dd 0.2 v dd (2.5 v) < 50 ns cs 90% do (tri-state to high) 10% 10% 90% 10% v tri-state < 50 ns
analog integrated circuit device data freescale semiconductor 11 33880 electrical characteristics typical electrical characteristics typical electrical characteristics figure 12. i pwr vs. temperature figure 13. sleep state i pwr vs. temperature figure 14. sleep state i pwr vs. v pwr figure 15. r ds(on) vs. temperature @ 250 ma figure 16. r ds(on) vs. v pwr @ 250 ma figure 17. current limit i out(lim) vs. temperature 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin (ma) 2 4 6 8 10 12 14 t a, ambient temperature ( c) all outputs on all outputs off v pwr @ 16 v 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin (ua) 2 4 6 8 10 12 14 t a, ambient temperature 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin ( a) 2 4 6 8 10 12 14 t a, ambient temperature ( c) v pwr @ 16 v 5.0 10 15 20 25 0 i pwr current into v pwr pin ( a) 10 20 30 40 50 60 70 v pwr t a = 25 c 0 25 50 100 125 -40 75 -25 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t a, ambient temperature ( c) v pwr @ 16 v r ds(on) ( ) r ds(on) ( ) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v pwr (v) 5.0 10 15 20 25 0 v pwr @ 16 v 0 25 50 100 125 -40 75 -25 i out(lim), current limit (a) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 t a, ambient temperature ( c) v pwr @ 16 v
analog integrated circuit device data 12 freescale semiconductor 33880 electrical characteristics typical electrical characteristics figure 18. open load detect current vs. temperature figure 19. open load detect current vs. v pwr figure 20. sleep state output leakage vs. v pwr 0 25 50 100 125 -40 75 -25 i oco, open load (ma) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t a, ambient temperature ( c) v pwr @ 16 v high-side configuration 5.010152025 0 i oco open load (ma) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v pwr (v) t a = 25 c 5.010152025 0 i out(lkg) , leakage current ( a) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v pwr (v) t a = 25 c
analog integrated circuit device data freescale semiconductor 13 33880 functional description introduction functional description introduction the 33880 is an eight-output hardware configurable power switch with 8-bit serial control. the 33880 incorporates smartmos ? 5 technology with cmos logic, bipolar/mos analog circuitry, and independent double diffused dmos power output transist ors. many benefits are realized as a direct result of using this mixed technology. a simplified internal block diagram of the 33880 is shown in figure 2 , page 2 . the 33880 device uses high-efficiency updrain power dmos output transistors exhibiting low drain-to-source on resistance values (r ds(on) 0.55 at 25 c) and dense cmos control logic. all out puts have independent voltage clamps to provide fast inductive turn-off and transient protection. operational bias currents of less than 4.0 ma on v dd and 12 ma on v pwr with any combination of outputs on are a direct result of using smartmos ? 5 technology. functional pin description chip select ( cs ) the system mcu selects the 33880 to communicate through the use of the cs pin. whenever the pin is in a logic low state, data can be transfe rred from the mcu to the 33880 device and vice versa. clocked-in data from the mcu is transferred from the 33880 shift register and latched into the power outputs on the rising edge of the cs signal. on the falling edge of the cs signal, output status information is transferred from the power out puts status register into the device's shift register. the falling edge of cs enables the do output driver. whenever the cs pin goes to a logic low state, the do pin output is enabled, thereby allowing information to be transferred from the 33880 to the mcu. to avoid any spurious data, it is essential the high-to-low transition of the cs signal occurs only when sclk is in a logic low state. system clock (sclk) the system clock pin (sclk) clocks the in ternal shift registers of the 33880. the serial data input (di) is latched into the input shift register on the falling edge of the sclk. the serial data output pin (do) shifts data out of the shift register on the rising edge of the sclk signal. false clocking of the shift register must be avoided to guarantee validity of data. it is essential the sclk pin be in a logic low state whenever chip select pin ( cs ) makes any transition. for this reason, it is recommended the sclk pin is commanded to a logic low state when the device is not accessed ( cs in logic high state). when the cs is in a logic high state, any signal at the sclk and di pin is ignored and the do is tri-stated (high impedance). data input (di) this pin is used for serial instruction data input. di information is latched into the input register on the falling edge of sclk. a logic high state present on di will program a specific output on. the specif ic output will turn on with the rising edge of the cs signal. conversely, a logic low state present on the di pin will program the output off . the specific output will turn off with the rising edge of the cs signal. to program the eight outputs of the 33880 device on or off , enter the di pin beginning with output 8, followed by output 7, output 6, and so on to output 1. for each falling edge of the sclk while cs is logic low, a data bit instruction ( on or off) is loaded into the shift register per the data bit di state. eight bits of entered information fills the shift register. to preserve data integrity, do not transition di as sclk transitions from a high to low logic state. data output (do) the serial data output (do) pin is the output from the shift register. the do pin re mains tri-state until the cs pin goes to a logic low state. all faults on the 33880 device are reported as logic [1] through the do data pin. regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. conversely, normal operating outputs with non-faulted loads ar e reported as logic [0]. the first positive transition of sclk will make output eight status available on do pin. each su ccessive positive clock will make the next output status avai lable. the di/do shifting of data follows a first-in-first-out protocol with both input and output words transferring the most significant bit (msb) first. enable (en) the en pin on the 33880 device either enables or disables the internal charge pump. the en pin must be high for this device to enhance the gates of the output drivers, perform fault detection, and reporting. active outputs during a low transition of the en pin will become active again when the en transitions high. if this feat ure is not required, it is recommended the en pin be connected to v dd . command input (in5 and in6) the in5 and in6 pins command inputs allowing outputs five and six to be used in pwm applications. in5 and in6 pins are ored with the spi communication input. for spi control of outputs five and six, the in5 and in6 pins should be grounded or held low by the microprocessor. in the same manner, when using the pwm feature the spi port must command the outputs off . maximum pwm frequency for each output is 2.0 khz.
analog integrated circuit device data 14 freescale semiconductor 33880 functional description logic power (vdd) the v dd pin supplies logic power to the 33880 device and is used for power-on reset (por). to achieve low standby current on v pwr supply, power must be removed from the v dd pin. the device will be in reset with all drivers off when v dd is below 3.9 v dc . open drain output (d1 ? d8) the d1 ? d8 pins are the open drain outputs of the 33880. for high-side drive configurations, the drain pins are connected to battery supply. in low-side drive configurations, the drain pins ar e connected to the low side of the load. all outputs may be configured individually as desired. when low-side drive is used, the 33880 limits the positive transient for inductive loads to 45 v. source output (s1 ? s8) the s1 ? s8 pins are the source outputs of the 33880. for high-side drive configuratio ns, the source pins are connected directly to the load. in low-side drive configurations the source is connected to ground. all outputs may be configured individually as desired. when high-side drive is used, the 33880 will lim it the negative transient for inductive loads to -20 v.
analog integrated circuit device data freescale semiconductor 15 33880 functional device operation operational modes functional device operation operational modes mcu interface description in operation, the 33880 functi ons as an eight-output serial switch serving as a microcontroller (mcu) bus expander and buffer, with fault management and fault reporting features. in doing so, the device directly relieves the mcu of the fault management functions. this device directly interfaces to an mcu using a serial peripheral interface (spi) for control and diagnostic readout. figure 21 and figure 24 , page 16 , illustrate the basic spi confi guration between an mcu and one 33880. figure 21. spi interface with microcontroller all inputs are compatible with 5.0 v and 3.3 v cmos logic levels and incorporate positive logic. whenever an input is programmed to a logic low state (<0.8 v) the corresponding output will be off. converse ly, whenever an input is programmed to a logic high state (>2.2 v), the output being controlled will be on. diagnostics are treated in a similar manner. outputs with a fault will feedback (via do) to the microcontroller as a logic [1] while normal operating outputs will provide a logic [0]. figure 22 illustrates the daisy chain configuration using the 33880. data from the mcu is clocked daisy chain through each device while the chip select ( cs ) bit is commanded low by the mcu. during each clo ck cycle output status from the daisy chain, the 33880 is being transferred to the mcu via the master in slave out (miso) line. on rising edge of cs data stored in the input register is then transferred to the output driver. figure 22. 33880 spi system daisy chain multiple 33880 devices can be controlled in a parallel input fashion using the spi. figure 23 illustrates 24 loads being controlled by three dedicated parallel mcu ports used for chip select. figure 23. parallel input spi control receive buffer parallel ports to logic 33880 mc68hcxx microcontroller do di cs sclk miso mosi shift regist er shift register mc68xx mcu with spi interface 8 outputs 8 outputs 8 outputs cs miso mosi parallel port sclk do di do di do di cs cs sclk sclk 33880 33880 33880 di sclk do cs parallel ports mosi miso sclk 8 outputs mc68xx microcontroller spi a b c di sclk do cs 8 outputs di sclk do cs 8 outputs
analog integrated circuit device data 16 freescale semiconductor 33880 functional device operation operational modes figure 24. data transfer timing
analog integrated circuit device data freescale semiconductor 17 33880 functional device operation operational modes power consumption the 33880 device has been designed with one sleep and one operational mode. in the sleep mode (v dd 2.0 v), the current consumed by the vpwr pin is less than 25 a. to place the 33880 in the sleep mode, turn all outputs off, then remove power from vdd and the en (enable) input pin. prior to removing power from the device, it is recommended all control inputs from the microcontroller are low. during normal operation, 4.0 ma will be drawn from the v dd supply and 12 ma from the v pwr supply. paralleling of outputs using mosfets as output swit ches allows the connection of any combination of outputs together. r ds(on) of mosfets have an inherent positive temp erature coefficient, providing balanced current sharing between outputs without destructive operation. the devi ce can even be operated with all outputs tied together. this mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. performance of para llel operation results in a corresponding decrease in r ds(on) while the outputs off open load detect currents and the output current limits increase correspondingly (by a fact or of eight if all outputs are paralleled). paralleling outputs from two or more different ic devices are possible but not recommended. fault logic operation fault logic of the 33880 devic e has been greatly simplified over other devices using spi communications. as command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the mcu. regardless of the conf iguration, with no outputs faulted, all status bits being received by the mcu will be zero. when outputs are faulted (off st ate open circuit or on state short circuit / overtemperature), the status bits being received by the mcu will be one. the distinction between open circuit fault and short circuit / overtemperature is completed via the command word. for example, when a zero command bit is sent and a one fault is received in the following word, the fault is open / short-to-battery for high-side drive or open / short to ground for low-side drive. in the same manner, when a one command bit is sent and a one fault is received in the following word the fault is a short-to-ground / overtemperature for high-side drive or short-to-battery / overtemperature for low-side drive. the timing betw een two write words must be greater than 300 s to allow adequate time to sense and report the proper fault status. spi integrity check it is recommended that one check the integrity of the spi communication with the initial power-up of the vdd and en pins. after initial sy stem start-up or reset, the mcu will write one 16-bit pattern to the 33880. the first eight bits read by the mcu will be the fault st atus of the outputs, while the second eight bits will be the first byte of the bit pattern. bus integrity is confirmed by the mcu receiving the same bit pattern it sent. please note that the sec ond byte the mcu sends to the device is the command byte and will be transferred to the outputs with rising edge of cs . overtemperature fault overtemperature detect and shutdown circuits are specifically incorporated for each individual output. the shutdown following an over temperature condition is independent of the system clock or any other logic signal. each independent output shuts down at 155 c to 185 c. when an output shuts down due to an overtemperature fault, no other outputs are affected. the mcu recognizes the fault by a one in the fault status register. after the 33880 device has cooled below the switch point temperature and 15 c hysteresis, the output will activate unless told otherwise by the mcu via spi to shut down. overvoltage fault an overvoltage condition on the vpwr pin will cause the device to shut down all output s until the overvoltage condition is removed. when the overvoltage condition is removed, the outputs will resume their previous state. this device does not detect an overvoltage on the vdd pin. the overvoltage threshold on the vpwr pin is specified as 25 v to 30 v with 1.0 v typical hysteresis. a vpwr overvoltage detect is global , causing all outputs to be turned off. output off open load fault an output off open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). the output off open load fault is detected by comparing the drain-to-source voltage of the specific mosfet output to an internally generated reference. each output has one dedicated comparator for this purpose. an output off open load fault is indicated when the drain- to-source voltage is less than the output threshold voltage (v thres ) of 1.0 v to 3.0 v. hence, the 33880 will declare the load open in the off state when the v ds is less than 1.0 v. this device has an internal 650 a current source connected from drain to source of the output mosfet. this prevents either configuration of the driver from having a floating output. to achieve low sleep mode quiescent currents, the open load detect curr ent source of each driver is switched off when v dd is removed. during output switching, especi ally with capacitive loads, a false output off open load fault may be triggered. to prevent this false fault from bei ng reported, an internal fault filter of 100 s to 300 s is incorporated. a false fault reporting is a function of the load impedance, r ds(on) , c out of the mosfet, as well as the supply voltage, v pwr . the rising edge of cs triggers the built-in fault delay timer. the timer will time out before the fault comparator is enabled and the fault is detected. once the condition causing the open load fault is removed, the device will resume normal operation. the open load fault however, will be latched in the output do register for the mcu to read.
analog integrated circuit device data 18 freescale semiconductor 33880 functional device operation operational modes shorted load fault a shorted load (overcurrent) fault can be caused by any output being shorted directly to supply or an output causing the device to current limit (linear short). there are two safety circuits progressively in operation during load short conditions providing system protection: 1. the device?s output current is monitored in an analog fashion using sensefet ? approach and current limited. 2. the device?s output therma l limit is sensed and when attained causes only the spec ific faulted output to shut down. the output will remain off until cooled. the device will then reassert th e output automat ically. the cycle will continue until the fault is remove or the command bit instructs the output off. undervoltage shutdown an undervoltage v dd condition will result in the global shutdown of all outputs. the undervoltage threshold is between 3.9 v and 4.6 v. when v dd goes below the threshold, all outputs are tur ned off and the fault status (fs) register is cleared. as v dd returns to norma l levels, the fs register will resume normal operation. an undervoltage condition at the vpwr pin will not cause output shutdown and reset. when v pwr is between 5.5 v and 9.0 v, the output will operate per the command word. however, the status as reported by the serial data output (do) pin may not be accurate below 9.0 v v pwr . proper operation at v pwr voltages below 5.5 v cannot be guaranteed. output voltage clamp each output of the 33880 inco rporates an internal voltage clamp to provide fast turn-off and transient protection of each output. each clamp independently limits the drain-to-source voltage to 45 v for low-side drive configurations and -20 v for high-side drive configurations (see figure 25 ). the total energy clamped (e j ) can be calculated by multiplying the current area under the current curve (i a ) times the clamp voltage (v cl ). characterization of the output clamps, using a single pulse non-repetitive method at 0.3 a, indicates the maximum energy to be 50 mj at 150 c junction temperature per output. figure 25. output voltage clamping spi configurations the spi configuration on the 33880 device is consistent with other devices in the oss family. this device may be used in serial spi or parallel spi with the 33291 and 33298. different spi configurations may be provided. for more information, contact analog products division. reverse battery the 33880 has been designed with reverse battery protection on the vpwr pin. however, the device does not protect the load from reverse battery. during the reverse battery condition, current will flow through the load via the output mosfet substrate diode. under this circumstance relays may energize and lamps will turn on. if load reverse battery protection is desired, a diode must be placed in series with the load. current area (i a ) clamp energy (e j = i a x v cl ) clamp energy (e j = i a x v cl ) drain voltage source voltage time time drain-to-source clamp voltage (v cl = 45 v) drain current (i d = 0.3 a) gnd gnd v bat drain-to-source on voltage (v ds(on) ) drain-to-source on voltage (v ds(on) ) current area (i a ) source current (i s = 0.3 a) source clamp voltage (v cl = -20 v)
analog integrated circuit device data freescale semiconductor 19 33880 functional device operation logic commands and registers logic commands and registers on each spi communication, an 8-bit command word is sent to the 33880 and an 8-bit fault word is received from the 33880. the most significant bit (msb) is sent and received first (see below). command register definition: 0 = output command off 1 = output command on fault register definition: 0 = no fault 1 = fault. msb lsb out8 out7 out6 out5 out4 out3 out2 out1 table 6. fault operation serial output (so) pins reports overtemperature fault reported by serial output (do) pin. overcurrent do pin reports short to battery /supply or overcurrent condition. output on open load fault not reported. output off open load fault do pin reports output off open load condition. device shutdowns overvoltage total device shutdown at v pwr = 25 v to 30 v. resumes normal operation with proper voltage. all outputs assuming the previous st ate upon recovery from overvoltage. overtemperature only the output experiencing an overtemperature f ault shuts down. output assumes previous state upon recovery from overtemperature.
analog integrated circuit device data 20 freescale semiconductor 33880 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using ? 98asb42345b ?. dimensions shown are provided for reference only. eg suffix (pb-free) 28-pin plastic package 98asb42345b rev g
analog integrated circuit device data freescale semiconductor 21 33880 packaging package dimensions package dimensions (continued) eg suffix (pb-free) 28-pin plastic package 98asb42345b rev g
analog integrated circuit device data 22 freescale semiconductor 33880 packaging package dimensions package dimensions (continued) ew suffix (pb-free) 32-pin plastic package 98asb42345b rev b
analog integrated circuit device data freescale semiconductor 23 33880 packaging package dimensions package dimensions (continued) ew suffix (pb-free) 32-pin plastic package 98asb42345b rev b
analog integrated circuit device data 24 freescale semiconductor 33880 revision history revision history revision date description of changes 4.0 6/2006 ? implemented revision history page ? converted to freescale format and adjusted content to prevailing form and style 5.0 6/2007 ? removed mc33880eg/r2 and mc33880ek/r2 from the ordering information and added mcz33880eg/r2 and mcz33880ew/r2. ? added peak package reflow temperature during reflow (8) , (9) ? updated data sheet to current format. 6.0 5/2008 ? changed 32 pin soicw, pins 8, 9, 24, 25 from gnd to tgnd on page 4. 7.0 1/2009 ? corrected notes for peak package reflow in maximum rating table. 8.0 5/2012 ? removed mcz33880eg from the ordering information and added MC33880PEG ? removed mcz33880ew from the ordering information added mc33880pew ? removed mc33880dw and mc33880dwb ? removed dw and dwb suffix ? updated freescale form and style
document number: mc33880 rev. 8.0 5/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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